​Yesterday we noted the $16.5b deal that Samsung (005930.KS) had recently signed with Tesla (TSLA) that will be a linchpin for the company’s new Taylor, Texas semiconductor fab.  Within hours of the announcement, speculation has begun as to Samsung’s additional plans for the fab, now that they have secured a large customer, other than the company itself.  Aside from the potential for a second fab and R&D center with a $24b price tag, that have been rumored to be in Samsung’s long-term plans, recently it has been ventured that Samsung is considering adding a $7b advanced packaging line to the current campus, in order to maintain local production.  Without such a line, Samsung would have to ship processed chips back to Korea for packaging.
One of Samsung’s OSAT partners, Amkor (AMKR), is building what will be the largest advanced packing facility in the US in Peoria, AZ but that facility will not be in mass production until late 2027 or early 2028, and we doubt Samsung could build out its own advanced packaging lines much earlier than that, so for the time being, even if Samsung does commit to an advanced packaging line, we expect the chip packaging for 2026 products will take place in Korea.
It has been thought that the Tesla deal gained traction as Samsung was able to bring its 2nm/3nm yields over 30%, which had been a stumbling block for Samsung in the past.  Progress on that front continues with some estimating near 40% currently, although Samsung has not officially confirmed any yield information.  Samsung seems to be more focused on improving 2nm yields than 3nm, likely to better compete with Taiwan Semi (TSM), whose N2 node (2nm) yields are thought to be in the range of 65%.  TSM is expected to be in mass production at the N2 node in the 2nd half of this year as is Samsung. 
Still up for grabs is the Qualcomm (QCOM) Snapdragon 8 Gen 5 chipset order expected next year.  While Samsung was the producer of the Qualcomm Snapdragon 8 Gen 1 back in 2022, Samsung’s yield issues pushed Qualcomm to shift production to TSM for the Gen 2 (2023), the Gen 3 (2024), and the current Gen 4 (2025), although it looks that there is potential for Samsung to participate in the Gen 5 as a co-supplier with TSM.  While shared, if such a deal were signed, it would be a major step toward Samsung’s foundry being able to directly compete with TSM and to regain much of the cache that it has lost over the last few years.  Both foundries have produced 2nm prototypes for Qualcomm’s evaluation, who has been hinting that they are considering a dual-sourcing strategy for the Gen 5.

January 2018 was the peak of the last memory cycle.  Then began a decline that continued through the year, a result of a significant amount of capacity oversupply.  The decline continued in 2019, with a slight recovery during 2020 due to COVID work-from-home demand and in 2021 (through the 1st half) that demand source continued.  In the back half of 2021 however COVID related demand began to wane, and DRAM prices began to slide again, and 2022 saw DRAM prices almost in freefall.  Toward the end of 2022 the key DRAM suppliers began to make investment and production cuts and in 2023 they began to make substantial cuts to reduce inventory that had been building for many quarters, leading to a gradual but steady recovery through mid-2024.

The AI wave began to give DRAM manufacturers relief last year which has continued into 2025 as we have noted previously, but with a vengeance, and by mid-year weekly double digit price increases were becoming common.  Over the last month, while prices have not declined they are no longer rising, having flattened for the last 6 weeks.  That said, projections for 3Q are for another 10% to 15% price increase for ‘generic’ DRAM and a 15% to 20% increase when including HBM.  Expectations for NAND in 3Q are more moderate but still project a 5% to 10% increase for the quarter.
Much rests on HBM as it is the current growth engine for the DRAM market with sales expected to almost double this year, and while AI continues to drive the HBM market, estimates, even those more than 5 years out continue to increase.  The enthusiasm behind AI growth, which should drive HBM products like DDR5 are also dragging along increased pricing for mainstream and legacy products like DDR4, which do not have the demand pull from AI.  In fact the price increases in DDR4 and similar memory products is also due to constrained supply as memory producers shift more production capacity to high-end HBM products which generate sales that give the share gains that memory manufacturers are striving for, despite the mantra that the industry is now focused on profitability over share.
The question then becomes whether the capacity and production management that DRAM suppliers are currently working under is enough to satisfy their desire for profits and share or will the desire for bragging rights drive the same cyclical expansion that devastated pricing during the last cycle?  One would like to think that the memory of severe price reductions would be fresh enough in their memories (sorry) that they might avoid the capacity expansion that caused the problem, but business is business and shareholders are shareholders, and the demands of same tend to cause memory loss (sorry again). 
As it turns out all three major memory producers have announced plans for capacity expansion.  Of course it is justified by the fact that most of that capacity is oriented toward HBM where both short-term and long-term estimates are rapidly increasing.  However, as in every cycle there are always estimates that justify an almost infinite growth path, as is the case for HBM and AI generally.  Even the perturbation of DeepSeek’s (pvt)  low-cost training model made little difference to memory pricing on both short and long term memory capacity plans, so we are left to watch the tea leaves and wonder whether the current memory price plateau has meaning or whether it is just another step in the stairway to the stars.  We know that recent capacity increase plans will take a number of years to implement, which those who see the glass half full look at as time needed to build even more HBM demand, while we expect the scenario that the memory business will be facing by the time that new capacity is in full production will be far different than it is today.

Samsung Electronics (005930.KS) announced that it had received a semiconductor contract with an undisclosed “large global company” worth 22.764 trillion won or ~$16.544 billion US.  The value of the contract is equal to 7.6%  of Samsung’s sales in 2024  and will run from 7/24/25 to 12/31/33.   While details were not given in the Samsung release, speculation is that Tesla (TSLA) is the customer and Elon Musk confirmed that Samsung is currently producing the A14 chip (7nm) and will be producing the A16 (2nm), although TSMC (TSM) will be producing the A15 (3nm), which has just completed the design phase in Taiwan and Arizona and is slated for production late next year.
The A16 is expected to be produced at Samsung’s Taylor, Texas fab, which is scheduled to begin production in 2H next year.  The Tesla A16 evaluation is loosely scheduled for 2H 2027.  Interestingly, Musk indicated that one factor in the contract decision was the fact that Samsung agreed to allow Tesla to assist in “maximizing manufacturing efficiency” at the fab.  Musk indicated, “I will walk the line personally to accelerate the pace of progress as the fab is conveniently located not far from my house.” (~40mi from what we can see).   While the contact amount was specified in the formal release, Musk indicated that it was a ‘minimum’ and gives Samsung’s new fab a substantial revenue base.

​Yesterday the governor of Michigan announced that a $55b semiconductor manufacturing project that was supposed to bring 10,000 jobs to Mundy Township had been cancelled .  The project, one of the largest economic investments in Michigan history, was to be the home of a SanDisk’s (SNDK) 1,300 acre mega site in Mundy Township in Genesee County that was to be focused om NAND Flash technology development and production.  Unfortunately the state has already spent $260m to acquire and prepare the site for the project.
Sandisk was offered over $6.2b in incentives with almost $2b in cash grants, along with $250m in workforce development funding and $3.75b in tax breaks, including a 50 year property tax abatement.  SanDisk is in their quarterly quiet period and has made no official comment, but as expected, both parties have blamed each other for the project failure.  The state expects to continue to promote the site to other advanced technology companies.

Given the volatile nature of the US/China tariff situation it has been obvious that not only have component suppliers been pulling in orders to beat on-again-off-again tariffs, but consumers, already burdened by high inflation and recession fears, have been a bit more cautious than usual about making purchases.  According to Tech Insights, high DAO inventory levels are coming down a bit but demand for most semiconductor components remains weak, while Ai related component demand continues at a strong pace.  Tech Insights has come up with two scenarios for the 2025/2026 semiconductor space after lower their earlier (March) forecast in April.  The two scenarios, moderate impact and severe impact, show how much the growth for 5 semiconductor type categories could be affected by a resumption of the more severe tariffs that were put in place and then postponed recently,
Tech Insights current expectations are now between the April forecast and the moderate scenario as negotiations continue, but the more severe scenario could occur if negotiations fail before the July deadline.  The current forecast and two scenarios are as follows:

​The table below shows the current growth forecast for  a number of semiconductor  categories for 2025 and 2026 and by how much that growth will be decreased for each semiconductor type (and total) for both years, under both scenarios.  The 2025 total growth forecast is for 14% growth.  Under the ‘moderate’ scenario, that growth would be decreased by 5.3% to 8.7% growth and under the more severe scenario it would be decrease from 14% by 10.4% to 3.6% growth.  In 2026, the current forecast calls for 9% overall growth.  Under the ‘moderate’ scenario for 2026 growth  would de decreased by 17.2% to negative 8.1% growth and under the severe scenario that 9% growth would decline by 34% to negative 25% growth.  Table 2 shows the same scenarios for the semiconductor equipment segment and their impact, while Table 3 shows which products would be the most affected by semiconductor tariffs from both a BOM standpoint and from the share of semiconductor sales.

To take the impact of semiconductor tariffs a bit further, we look  at a McKinsey report that shows semiconductor share of product BOM, essentially quantifying the impact of semiconductor tariffs on various CE products.  We arranged the table according to the sales value.  While SSDs are only ~5% of semiconductor sales value total, the table shows that 90% of the BOM is semiconductors, making them the most affected product category for semiconductor tariffs, but from a total value standpoint data center server racks represent 25% of all semiconductor sales value while having an 81% semiconductor BOM.  Making DCS the most impacted by semiconductor tariffs of all CE product categories.

​Needless to say at least some resolution to the trade issues must occur this year and one that is sustainable for at least 2025 and 2026.  If another postponement or interim solution is proposed it will just serve to continue the lack of long-term planning that seems to be the case across the component business, other than in the AI space, which will lead to more difficult circumstances in the out years of this administration, when negotiators will be doing everything possible to run out the clock before committing to major capital spending or purchase agreements.  Without at least some significant agreements on lower tariffs between the US and China, we expect both countries will see slower than expected semiconductor growth over the next few years. 

In November of 2021 Samsung Electronics and the city of Taylor, Texas signed an agreement  for a large semiconductor project, after Samsung received offers from a number of cities around the US as part of the country’s $6.4 b CHIPS ACT designed to bring semiconductor production back to the US.  The first of two plants and support buildings and infrastructure were originally slated to be completed during the 2nd half of last year.  In July of 2022 the government of Taylor expanded the tax incentive agreements, however by the end of 2023 Samsung announced that there would be a delay in the opening of the plant, moving it from 2H 2024 to 2025, although it was thought that Samsung was also upgrading the plant to 2nm production to compete with other foundries.
However, as it is rare that plans, especially for such a large project, meet early timelines, Samsung’s construction has been slower than expected and the plant 1 start up date was pushed back again to 2026 as construction has been on hold for the last few months a result of a weak semiconductor market.  This has caused the Taylor city government to amend its original tax incentive plans, which were a bit open ended, to push Samsung more intensely to move forward with the project.  Taylor made the following changes to the plan:

• Samsung will start bringing in process equipment by the end of 2026
• Taylor capped its reimbursements to Samsung for plan reviews and inspections at $9m, down from $25m previously.
• Samsung must complete 6m ft2 of permanent and temporary building space by the end of 2026 and another 1m ft2 by 2028.

While these are certainly not draconian measures, they do indicate considerable frustration with the pace of Samsung’s project development, especially given how aggressive other cities and regions were when wooing Samsung to a new US location (Genesee County, NY – Goodyear, AZ – Queen Creek, AZ – Austin, TX).  Samsung is facing a weak semiconductor market , a variable tariff situation, weak consumer demand, and an administration that looks to reduce previous administration semiconductor spending, making the large capital expenditures needed for this project problematic, but will have to meet at least these new goals if they are to receive the tax breaks they need to control costs.  That said, the bigger question is whether the current administration will rescind already promised CHIPS capital, which would be a far more onerous situation than the amended Taylor tax incentive plans.  Of course, Samsung can always decide to sell the plant and have someone make it into an AI data center…

video of plant under construction
https://www.instagram.com/reel/C_Y-eyWxYBd/?utm_source=ig_web_copy_link

As the US and China seem to be negotiating over trade and tariff issues, the US Department of Commerce’s Bureau of Industry & Security is said to have sent formal letters to at least three leading EDA firms directing them to halt support of their EDA tools to mainland China.  The three firms, Siemens (SIE.XE), Synopsys (SNPS), and Cadence (CDNS) who represent almost 75% of the EDA tool market, dominate China’s semiconductor design tool market, with local firms representing only ~11.5%.  Siemens, with the smallest share of the three (13%) has already blocked its EDA related sites in China, while both Synopsys and Cadence are awaiting official confirmation and details, although there are questions about the validity of the notifications themselves.
The notifications were said to state that the companies should not be selling EDA equipment to Chinese entities without a license, essentially setting up a review process for all EDA sales and support into China, but some in the administration suggest that while it seems like an outright ban on EDA sales to China, decisions will be made on a case-by-case basis.  EDA tool sales have already been banned for nodes below 3nm (since 2022), but it is thought that the new notification extends that ban to 7nm, which is the level at which China’s leading foundry SMIC (981.HK) has been able to reach commercially, albeit in limited quantities.  Foundries outside of China have been producing at 3nm, typically using EUV tools that are unable to be sold to Chinese customers, leaving them with DUV tools as an alternative, a more complex and costly process.  Further restricting design tools will limit China’s ability to move to 5nm and below, even if they are able to use existing DUV process equipment as the design process will be limited to existing tools designed for more mature nodes and those developed exclusively on the mainland.
While we expect this latest round of potential regulations and limitations might be the administration’s latest negotiating ploy, rarely are these kinds of limitations rolled back, as the government can use its license granting power to pick and choose what and when it will allow such equipment to be sold to China.  The threat is what matters here, and we expect the timing of the potential EDA rule tightening is a way to ‘convince’ China that the US means business and they better come to the table willing to make concessions.  The administration says the stepped up EDA ban is just part of its longer-term investigation of the effects of China’s progress in the semiconductor space, but it seems a bit more transparent than that to us.

After the Chinese gut punch the Ai industry received this week, there was another impactful event that pointed toward China’s relentless push toward becoming a world-class player in the semiconductor space, despite the US government’s steps to keep China from competing.  ChangXin Memory Technologies (pvt), China’s leading memory producer, has released its first 16Gb DDR5 chip (already produces DDR3L, DDR4, LPDDR4X, and LPDDR5).  Earlier versions (G1 – G3) were produced on 23.8nm and 18nm nodes, or the equivalent of D2y and D1x generations.  As DDR5 has surpassed DDR4 in terms of volume, this gives China there own DDR5 product that will compete against Samsung Electronics (005930.KS), SK Hynix (000660.KS), and Micron (MU).
The three non-Chinese DDR5 producers began mass production of DDR5 in 2021 and current products have a feature size between 12nm and 14nm, which gives them a three-year lead of CXMT.  However CMXT was able to skip the 17nm node step to reduce development time and is able to give the product a higher bit density than both Samsung’s and SK Hynix’s products (Micron is slightly higher).  Higher bit density allows for greater memory capacity without increasing the chip size.  The CMTX chips were found in a teardown of a Chinese high-performance solid-state drive that is the first SSD to be able to store 20Gb/mm2 by stacking 16 CMXT DDR5 chips.

​We do not make the mistake if taking this event to mean that China’s home-grown memory industry has caught up with current supplier technology, but it does indicate that China continues to shorten the lead its competitors have, even considering the roadblocks that have been put in its way.  Whie the semiconductor space represents a higher level of complexity compared to the display space, comparisons can be made, and earlier this week, the afront to the US dominance of the Ai world lends a bit more credibility to China’s overall efforts in technology.  Sometimes when you poke the bear, it bites back.

NAND Flash is an essential memory product used in a variety of consumer and enterprise products, particularly smartphones and Solid-State Drives.  It is comprised primarily of MOSFET Transistors that trap electrons within the gate of the transistor.  The presence or absence of electrons indicates a 0 or 1, and while RAM (Random Access Memory) is short-term storage, NAND is considered long-term storage and will hold its gate state without power, making them ideal of Solid State Drives.  There are only a few NAND flash producers, with Samsung Electronics (005930.KS) the leader for many years.
As the leader, Samsung tends to set the tone for the industry, and in March of 2024, a few months after a peak was reached in NAND pricing and inventory had built up to the point where an oversupply situation was obvious, Samsung cut NAND production by almost 50%.  Relatively quickly other producers followed and within a short time NAND prices stabilized and began to rise again.  Unfortunately, the slowdown in smartphone demand and a somewhat surprising weakening in enterprise SSD demand (given the AI hype) made NAND prices unable to hold early 2024 gains and a second decline began in 2H.
Samsung’s poor results in 4Q were the result of that weakness, and the company has decided to cut production at its fab in Xian, China, its largest NAND production fab, by more than 10%, from 200k wafers/month to 170k, and will also cut NAND production at two lines at its fabs in Hwaseong, South Korea.  Typically, one would expect the other NAND flash producers to follow relatively quickly but it seems that Samsung is the first to set the tone of trying to break the downward NAND pricing cycle this year, at least thus far.  While it has been a short time since Samsung signaled the NAND production cuts, we expect others to follow, however, given the continuing hype around AI and its positive influence on data center capacity and the need for SSD’s, it might prove more difficult to convince others to participate, particularly Samsung’s biggest rival in the NAND space, SK Hynix ((000660.KS), who has been and continues to add capacity for high-end NAND products.
 

NAND Flash is an essential memory product used in a variety of consumer and enterprise products, particularly smartphones and Solid-State Drives.  It is comprised primarily of MOSFET Transistors that trap electrons within the gate of the transistor.  The presence or absence of electrons indicates a 0 or 1, and while RAM (Random Access Memory) is short-term storage, NAND is considered long-term storage and will hold its gate state without power, making them ideal of Solid State Drives.  There are only a few NAND flash producers, with Samsung Electronics (005930.KS) the leader for many years.
As the leader, Samsung tends to set the tone for the industry, and in March of 2024, a few months after a peak was reached in NAND pricing and inventory had built up to the point where an oversupply situation was obvious, Samsung cut NAND production by almost 50%.  Relatively quickly other producers followed and within a short time NAND prices stabilized and began to rise again.  Unfortunately, the slowdown in smartphone demand and a somewhat surprising weakening in enterprise SSD demand (given the AI hype) made NAND prices unable to hold early 2024 gains and a second decline began in 2H.
Samsung’s poor results in 4Q were the result of that weakness, and the company has decided to cut production at its fab in Xian, China, its largest NAND production fab, by more than 10%, from 200k wafers/month to 170k, and will also cut NAND production at two lines at its fabs in Hwaseong, South Korea.  Typically, one would expect the other NAND flash producers to follow relatively quickly but it seems that Samsung is the first to set the tone of trying to break the downward NAND pricing cycle this year, at least thus far.  While it has been a short time since Samsung signaled the NAND production cuts, we expect others to follow, however, given the continuing hype around AI and its positive influence on data center capacity and the need for SSD’s, it might prove more difficult to convince others to participate, particularly Samsung’s biggest rival in the NAND space, SK Hynix ((000660.KS), who has been and continues to add capacity for high-end NAND products.
 

The January 1 earthquake that hit the coast of Japan on January 1 caused severe damage to the Northern Coast of Ishikawa Prefecture, with the epicenter about 26 miles northeast of the town of Anamizu.  This puts the Japan Display (6740.JP) Ishikawa LCD fab approximately 55 miles from the epicenter of the 7.5 magnitude quake, and while the magnitude at that distance was closer to 5.0 to 5.5 on the Richter scale, it was enough to cause a number of semiconductor fabs nearby to be shut down for inspection, particularly the Toshiba (pvt) Kaga fab, which is ~9.3 miles south west of the JDI fab, and has given no estimate for when it might reopen.  While Japan Display has not commented on the status of the Ishikawa fab, we expect automated sensors at the fab, similar to those at the Toshiba Semiconductor fab, would have triggered an automated shutdown of sensative equipment to prevent damage and closing water and gas lines.  If the impact of the quake was limited to a general shutdown, we would expect the production loss to be limited to ~2 days and the loss of some product that was on the line when the shutdown occurred, so the overall impact to JDI, at least at this juncture, is minimal.
The semiconductor fabs in Ishikawa Prefecture, in most cases, were automatically shut down and would require full inspection before restarting.  Tower Semiconductor (TSEM), which has two fabs in Ishikawa Prefecture stated, “There was no impact or damage to the buildings and only minor damage to the facilities which had no impact on operations. The dedicated staff and response teams have worked to ensure operational safety and stability. Tools requalification is underway, combined with efforts to efficiently repair any damage to fab tools and in-line materials, while utilizing all available resources to minimize any potential disruptions to manufacturing and customer service.” 
Taiyo Yuden (6976.JP), a supplier of MLCCs with a ~5% share stated, “No injuries to our group employees have been confirmed. In addition, our group's production bases, no major damage was confirmed to the building or production equipment. Production is expected to resume after equipment inspection work is through”. No word from Global Wafers (6488.TT), who has two production facilities about 100 miles from the epicenter, although local sources indicate that wafer production was halted and the lines are undergoing full inspection, with the same for Shin-Etsu (4063.JP), although silicon wafer growth using the CZ method is very sensative to vibration and can cause uneven crystal growth or stress defects.  While 4” silicon wafers can be grown in 3 to 5 days, 8” wafers can take between 7 to 14 days, and 12” wafers between 14 to 28 days, so it will take quite a while to assess the damagefacing these wafer fabs.
All in, while the damage to smaller towns in northern Ishikawa was significant, most production facilities seem to be relatively unaffected, other than the typical automated shutdown, inspection  and restart, which we expect, for those with no significant damage, will take a few days to complete.  The loss of WIP is still unknown, and in the case of wafers production, could turn out to be a bit more significant, but it would seem that production losses will be limited to a week to 10 days on average so far.  Not a disaster for the display and semiconductor industry, but not a happy new year in Ishikawa for others.